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CDCF2510 3.3-V Phase-Lock Loop Clock Driver

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Description

CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS628D * APRIL 1999 * REVISED DECEMBER 2004 D Use CDCVF2510A as a Replacement for thi.
The CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

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Applications

* D Distributes One Clock Input to One Bank of 10 Outputs D Output Enable Pin to Enable/Disable All 10 Outputs D External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input D On-Chip Series Damping Resistors D No External RC Network Required D Operates at 3.3 V PW PACKAGE

CDCF2510 Distributors

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