CDCF5801A

CLOCK MULTIPLIER

Texas Instruments

CDCF5801A Features

* Low-Jitter Clock Multiplier: ×1, ×2, ×4, ×8

* Fail-Safe Power Up Initialization

* Programmable Bidirectional Delay Steps of 1.3 mUI

* Output Frequency Range of 25 MHz to 280 MHz

* Input Frequency Range of 12.5 MHz to 240 MHz

* Low Jitter Generation

CDCF5801A General Description

The CDCF5801A provides clock multiplication from a reference clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as th.

CDCF5801A Datasheet (382.20 KB)