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CDCF5801A CLOCK MULTIPLIER

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Description

CDCF5801A www.ti.com SCAS816 * MARCH 2006 CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT .
The CDCF5801A provides clock multiplication from a reference clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB w.

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Features

* Low-Jitter Clock Multiplier: ×1, ×2, ×4, ×8
* Fail-Safe Power Up Initialization
* Programmable Bidirectional Delay Steps of 1.3 mUI
* Output Frequency Range of 25 MHz to 280 MHz
* Input Frequency Range of 12.5 MHz to 240 MHz
* Low Jitter Generation

Applications

* Video Graphics
* Gaming Products
* Datacom
* Telecom
* Noise Cancellation Created by FPGAs DBQ PACKAGE (TOP VIEW) VDDREF 1 REFCLK 2 VDDP 3 GNDP 4 GND 5 LEADLAG 6 DLYCTRL 7 GNDPA 8 VDDPA 9 VDDPD 10 STOPB 11 PWRDNB 12 24 P0 23 P1 2

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