* 1 Integrated Low-Noise Clock Generator Including PLL, VCO, and Loop Filter
* Two Low-Noise 100-MHz Clocks (LVPECL, LVDS, or pair of LVCMOS)
* Support for HCSL Signaling Levels (AC-Coupled)
* Typical Period Jitter: 21 ps pk-pk
* Typical Random Jitter: 510 fs R
CDCM9102
1.42 MB
Low-noise two-channel 100-mhz clock generator.
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Reference Design
CDCM9102
SCAS922A
* FEBRUARY 2012 .
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