CDCV850 Datasheet (Texas Instruments) - 2.5-V Phase Lock Loop Clock Driver

CDCV850, 2.5-V Phase Lock Loop Clock Driver

GND 18 Y3 19 31 GND 30 Y8 The CDCV850 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs Y3 20 VDDQ 21 Y4 22 Y4 2

CDCV850, CDCV850I 2.5ĆV PHASE LOCK LOOP CLOCK DRIVER WITH 2ĆLINE SERIAL INTERFACE SCAS647B OCTOBER 2000 REVISED DECEMBER 2002 D Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM DGG PACKAGE (TOP VIEW) Applications D Spread Spectrum Clock Compatible D Operating Frequency: 60 to 140 MHz D Low Jitter (cyc cyc): ±75 ps D Distributes One Differential Clock Input to GND 1 Y0 2 Y0 3 VDDQ 4 Y1 5 48 GND 47 Y5 46 Y5 45 VDDQ 44 Y6 Ten Differential Outputs