CDCV857A Datasheet - Texas Instruments

CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER

The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). The clock outputs are controlled by th.

CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER D Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications D Spread Spectrum Clock Compatible D Operating Frequency: 60 to 180 MHz D Low Jitter (cyc cyc): ±50 ps D Distributes One Differential Clock Input to Ten Differential Outputs SCAS667A APRIL 2001 REVISED AUGUST 2002 D Three-State Outputs When the Input Differential Clocks Are <20 MHz D Operates From Dual 2.5-V Supplies D Available in a 48-Pin T.

CDCV857A Datasheet (829.53 KB)