CDCV855I Datasheet - Texas Instruments

CDCV855I 2.5-V PHASE-LOCK LOOP CLOCK DRIVER

The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to four differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs swi.

CDCV855, CDCV855I 2.5-V PHASE-LOCK LOOP CLOCK DRIVER D Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications D Spread Spectrum Clock Compatible D Operating Frequency: 60 MHz to 180 MHz D Low Jitter (cyc cyc): ±50 ps D Distributes One Differential Clock Input to Four Differential Clock Outputs D Enters Low Power Mode and Three-State Outputs When Input CLK Signal Is Less Than 20 MHz or PWRDWN Is Low D Operates From Dual 2.5-V Supplies D 28-Pin TSSOP Package D Con.

CDCV855I Datasheet (355.56 KB)