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CDCV855 2.5-V PHASE-LOCK LOOP CLOCK DRIVER

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Description

CDCV855, CDCV855I 2.5-V PHASE-LOCK LOOP CLOCK DRIVER D Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications D Spread Spect.
The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to four differe.

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Applications

* D Spread Spectrum Clock Compatible D Operating Frequency: 60 MHz to 180 MHz D Low Jitter (cyc
* cyc): ±50 ps D Distributes One Differential Clock Input to Four Differential Clock Outputs D Enters Low Power Mode and Three-State Outputs When Input CLK Signal Is Less Than 20 MHz or PWRDWN Is Low

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