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CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver

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Description

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCVF2505 SCAS640G * JULY 2000 * REVISED AUG.
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

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Applications

* Spread Spectrum Clock Compatible
* Operating Frequency: 24 MHz to 200 MHz
* Low Jitter (Cycle-to-Cycle): < |150 ps| (Over 66 MHz to 200 MHz Range)
* Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Used to Tune the Input-Output Delay)
* Three-

CDCVF2505 Distributors

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