CDCVF2509 Datasheet - Texas Instruments

CDCVF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509 operate.

CDCVF2509 Features

* 1

* Use CDCVF2509A (SCAS765) as a Replacement for This Device

* Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1

* Spread Spectrum Clock Compatible

* Operating Frequency 50 MHz to 175 MHz

* Static Phase Error Distribution at 66 MH

CDCVF2509 Datasheet (400.27 KB)