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CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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Description

CDCVF2510 www.ti.com SCAS638C * JULY 2001 * REVISED APRIL 2006 3.3-V PHASE-LOCK LOOP CLOCK DRIVER .
The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

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Features

* Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
* Spread Spectrum Clock Compatible
* Operating Frequency 50 MHz to 175 MHz
* Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps
* Jitter (cyc - cyc) at 66 MHz to 166

Applications

* Distributes One Clock Input to One Bank of 10 Outputs
* External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
* 25-Ω On-Chip Series Damping Resistors
* No External RC Network Required
* Operates at 3.3 V PW PACKAGE (TOP VIE

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