* 1
* 2 30 fs additive jitter (100 Hz to 20 MHz)
* Dual clock inputs
* Programmable output channels (0 to 1600 MHz)
* External synchronization
* Pin compatible family of clocking devices
* 3.15 to 3.45 V operation
* Package: 48 pin LLP (7.0 x 7.0
LMK01000
0.97 MB
1.6ghz high performance clock buffer divider.
LMK01000 www.ti.com SNAS437G FEBRUARY 2008 REVISED OCTOBER 2009 LMK01000 Family LMK01000 Family 1.6 GHz High Performance Clock .
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