LMK04011 Features
* 1
* 23 Cascaded PLLatinum™ PLL Architecture
* PLL1
* Phase Detector Rate of up to 40 MHz
* Integrated Low-Noise Crystal Oscillator Circuit
* Dual Redundant Input Reference Clock with LOS
* PLL2
* Normalized [1 Hz] PLL Noise Floor of 224 dBc/Hz
Datasheet Details
LMK04011, LMK04000
1.12 MB
Family low-noise clock jitter cleaner.
This datasheet PDF includes multiple part numbers: LMK04011, LMK04000.
Please refer to the document for exact specifications by model.
📁 Related Datasheet
LMK04010 Family Low-Noise Clock Jitter Cleaner (Texas Instruments)
LMK04000 Family Low-Noise Clock Jitter Cleaner (Texas Instruments)
LMK04000 Low-Noise Clock Jitter Cleaner (National Semiconductor)
LMK04001 Family Low-Noise Clock Jitter Cleaner (Texas Instruments)
LMK04002 Family Low-Noise Clock Jitter Cleaner (Texas Instruments)
LMK04031 Family Low-Noise Clock Jitter Cleaner (Texas Instruments)
LMK04031B Precision Clock Conditioners Low-Noise Clock Jitter Cleaner (National Semiconductor Corporation)
LMK04033 Family Low-Noise Clock Jitter Cleaner (Texas Instruments)
LMK04011 Distributor
