* 1
* 23 Cascaded PLLatinum™ PLL Architecture
* PLL1
* Phase Detector Rate of up to 40 MHz
* Integrated Low-Noise Crystal Oscillator Circuit
* Dual Redundant Input Reference Clock with LOS
* PLL2
* Normalized [1 Hz] PLL Noise Floor of 224 dBc/Hz
LMK04033
1.12 MB
Family low-noise clock jitter cleaner.
www.ti.com
LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033
SNOSAZ8J
* SEPTEMBER 2008
* REVISED SEPTEMBER 2011
LM.
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