* 1
* 23 Cascaded PLLatinum™ PLL Architecture
* PLL1
* Redundant Reference Inputs
* Loss of Signal Detection
* Automatic and Manual Selection of Reference Clock Input
* PLL2
* Phase Detector Rate up to 100 MHz
* Input Frequency-Doubler
LMK04102 Datasheet (817.92 KB)
LMK04102
817.92 KB
Family clock jitter cleaner.
www.ti.com
LMK04100, LMK04101, LMK04102, LMK04110 LMK04111, LMK04131, LMK04133
SNAS516B
* APRIL 2011
* REVISED NOVEMBER 2012
LMK0410.
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