* dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a
LMK04000
National Semiconductor
1.23 MB
Low-noise clock jitter cleaner.
LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs www.DataSheet4U.com July 24, 2009 LMK04000 Family Low-Noise Clock Jitter Cleaner.
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