* 1 Dual-loop PLL architecture
* Ultra low noise (10 kHz to 20 MHz):
* 48-fs RMS jitter at 1966.08 MHz
* 50-fs RMS jitter at 983.04 MHz
* 61-fs RMS jitter at 122.88 MHz
* 165-dBc/Hz noise floor at 122.88 MHz
* JESD204B support
LMK04616
2.32 MB
Ultra-low noise and low power jesd204b compliant clock jitter cleaner.
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LMK04616
SNAS663B
* MARCH 2017
* REVISED JULY 2.
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