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SN74SSQE32882 - 28-BIT TO 56-BIT REGISTERED BUFFER

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SN74SSQE32882 Product details

Description

ORDERING INFORMATION This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 Registered DIMMs up to DDR3-1333 with VDD of 1.5 V.All inputs are 1.5-V, CMOS-compatible.All outputs are 1.5-V CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications.Clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn, and DxODTn can each be driven with a different strength and skew to

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