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SN74SSQE32882 28-BIT TO 56-BIT REGISTERED BUFFER

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Description

SN74SSQE32882 www.ti.com SCAS857A * MARCH 2008 * REVISED OCTOBER 2008 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST ON.
ORDERING INFORMATION This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for opera.

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Features

* 1
* 2 JEDEC SSTE32882 Compliant
* 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 DIMMs
* Chip Select Inputs Prevent Data Outputs from Changing State and Minimize System Power Consumption
* 1.5-V Phase Lock Loop Clock Driver Buffers One Diffe

Applications

* DDR3 Registered DIMMs up to DDR3-1333

SN74SSQE32882 Distributors

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SN74SSQE32882 28-BIT 56-BIT REGISTERED BUFFER Texas Instruments
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