Datasheet4U Logo Datasheet4U.com

SN74SSQEA32882 28-Bit to 56-Bit Registered Buffer

📥 Download Datasheet Datasheet Preview Page 1

Description

SN74SSQEA32882 www.ti.com SCAS879B * JUNE 2009 * REVISED OCTOBER 2010 28-Bit to 56-Bit Registered Buffer With Address Parity Test On.
This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 register.

📥 Download Datasheet

Preview of SN74SSQEA32882 PDF
datasheet Preview Page 2 datasheet Preview Page 3

Features

* 1
* JEDEC SSTE32882 Compliant
* 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs
* CKE Powerdown Mode for Optimized System Power Consumption
* 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK

Applications

* DDR3 Registered DIMMs up to DDR3-1600
* DDR3L Registered DIMMs up to DDR3L-1333

SN74SSQEA32882 Distributors

📁 Related Datasheet

SN74S1051 SN74S1051R SN74S1051T SN74S350 SN74S557 SN74S558

📌 All Tags

SN74SSQEA32882 28-Bit 56-Bit Registered Buffer Texas Instruments
Texas Instruments SN74SSQEA32882-like datasheet
SN74SSQE32882
SN74SSQEB32882
SN74SSQEC32882
SN74SSTEB32866
SN74SSTU32864