SN74SSQEC32882
767.61kb
28-bit to 56-bit registered buffer. This 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDD
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SN74SSQE32882 - 28-BIT TO 56-BIT REGISTERED BUFFER
(Texas Instruments)
SN74SSQE32882
.ti. .
SN74SSQEA32882 - 28-Bit to 56-Bit Registered Buffer
(Texas Instruments)
SN74SSQEA32882
.ti.
SCAS879B – JUNE 2009 – REVISED OCTOBER 2010
28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four P.
SN74SSQEB32882 - 28-Bit to 56-Bit Registered Buffer
(Texas Instruments)
SN74SSQEB32882
.ti.
SCAS896-PUB – JUNE 2010
28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clo.
SN74SSTEB32866 - 1.5V/1.8V 25-BIT CONFIGURABLE REGISTERED BUFFER
(Texas Instruments)
SN74SSTEB32866
.ti. .
SN74SSTU32864 - 25-BIT CONFIGURABLE REGISTERED BUFFER
(Texas Instruments)
SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
D Member of the Texas Instruments
Widebus+ .
SN74SSTU32864C - 25-BIT CONFIGURABLE REGISTERED BUFFER
(Texas Instruments)
.ti.
FEATURES
• Member of the Texas Instruments Widebus+™ Family
• Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit .
SN74SSTUB32864 - 25-BIT CONFIGURABLE REGISTERED BUFFER
(Texas Instruments)
.ti.
SN74SSTUB32864
SCAS791A – OCTOBER 2006 – REVISED SEPTEMBER 2007
25-BIT CONFIGURABLE REGISTERED BUFFER
FEATURES
1
•2 Member of the Texas I.
SN74SSTUB32866 - 25-BIT CONFIGURABLE REGISTERED BUFFER
(Texas Instruments)
SN74SSTUB32866
.ti.
SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007
25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
FEATURES
.
SN74SSTV16859 - 13-BIT TO 26-BIT REGISTERED BUFFER
(Texas Instruments)
D Member of the Texas Instruments
Widebus Family
D 1-to-2 Outputs to Support Stacked DDR
DIMMs
D Supports SSTL_2 Data Inputs D Outputs Meet SSTL_2 Cl.
SN74SSTV32852 - 24-BIT TO 48-BIT REGISTERED BUFFER
(Texas Instruments)
D Member of the Texas Instruments
Widebus Family
D 1-to-2 Outputs Support Stacked DDR
DIMMs
D Supports SSTL_2 Data Inputs D Outputs Meet SSTL_2 Class.