TMS418160A Datasheet - Texas Instruments

TMS418160A DYNAMIC RANDOM-ACCESS MEMORIES

This data sheet is applicable to TMS418160As symbolized by Revision “E” and subsequent revisions as described in the device symbolization section. D Organization . . . 1 048576 by 16 Bits D Single 5-V Power Supply (± 10% Tolerance) D 1 024-Cycle Refresh in 16 ms D Performance Ranges: ACCESS ACCESS ACCESS TIME TIME TIME tRAC tCAC tAA MAX MAX MAX READ/ WRITE CYCLE MIN ’418160A-50 50 ns 13 ns 25 ns 90 ns ’418160A-60 60 ns 15 ns 30 ns 110 ns ’418160A-70 70 ns 18 ns 35 ns 130 ns D Enhance.

TMS418160A Features

* maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS418160A is offered in a 42-lead plastic surface-mount SOJ package (DZ suffix). This package is designed for

TMS418160A Datasheet (345.89 KB)