TPS51206 - 2-A Peak Sink / Source DDR Termination Regulator
The TPS51206 device is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output.
It is specifically designed for low-input voltage, low-cost, low-external component count systems where space is a key consideration.
The device maintains fast transient respo
TPS51206 Features
* 1 Supply Input Voltage: Supports 3.3-V Rail and 5-V Rail
* VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V
* VTT Termination Regulator
* Output Voltage Range: 0.5 V to 0.9 V
* 2-A Peak Sink and Source Current
* Requires Only 10-μF MLCC Output Capacitor
