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TPS51206 2-A Peak Sink / Source DDR Termination Regulator

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Description

Product Folder Order Now Technical Documents Tools & Software Support & Community TPS51206 SLUSAH1E * MAY 2011 * REVISED JULY 201.
The TPS51206 device is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output.

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Features

* 1 Supply Input Voltage: Supports 3.3-V Rail and 5-V Rail
* VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V
* VTT Termination Regulator
* Output Voltage Range: 0.5 V to 0.9 V
* 2-A Peak Sink and Source Current
* Requires Only 10-μF MLCC Output Capacitor

Applications

* DDR2, DDR3, DDR3L, and DDR4 Memory Power Supplies
* SSTL_18, SSTL_15, SSTL_135 and HSTL Termination

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