74AUP1G74 Datasheet (nexperia) - Low-power D-type flip-flop

74AUP1G74, Low-power D-type flip-flop

The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs.

Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the f

74AUP1G74 Features

* Wide supply voltage range from 0.8 V to 3.6 V

* CMOS low power dissipation

* High noise immunity

* Overvoltage tolerant inputs to 3.6 V

* Low static power consumption; ICC = 0.9 μA (maximum)

* Latch-up performance exceeds 100 mA per JESD 78 Class II