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74HC112 Dual JK flip-flop

74HC112 Description

74HC112; 74HCT112 Dual JK flip-flop with set and reset; negative-edge trigger Rev.4 * 11 January 2021 Product data sheet 1.General descr.
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop.

74HC112 Features

* Input levels:
* For 74HC112: CMOS level
* For 74HCT112: TTL level
* Asynchronous set and reset
* Specified in compliance with JEDEC standard no. 7A
* ESD protection:
* HBM JESD22-A114F exceeds 2000 V
* MM JESD22-A115-A exceeds 200 V

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