74HC4024-Q100 Datasheet - nexperia

74HC4024-Q100 7-stage binary ripple counter

The 74HC4024-Q100 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outpu.

74HC4024-Q100 Features

* Automotive product qualification in accordance with AEC-Q100 (Grade 1)

* Specified from -40 °C to +85 °C and from -40 °C to +125 °C

* Low-power dissipation

* Complies with JEDEC standard no. 7A

* CMOS input levels

* ESD protection:

* MIL-STD-

74HC4024-Q100-nexperia.pdf