74HC4020-Q100 Datasheet - NXP

74HC4020-Q100 14-stage binary ripple counter

The 74HC4020-Q100; 74HCT4020-Q100 are 14-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and.

74HC4020-Q100 Features

* Automotive product qualification in accordance with AEC-Q100 (Grade 1)

* Specified from 40 C to +85 C and from 40 C to +125 C

* Input levels:

* For 74HC4020-Q100: CMOS level

* For 74HCT4020-Q100: TTL level

* Complies with JEDEC standard no. 7A

* ESD protection:

74HC4020-Q100-NXP.pdf