74LVC1G175 Datasheet - nexperia

74LVC1G175 Single D-type flip-flop

The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on .

74LVC1G175 Features

* Wide supply voltage range from 1.65 V to 5.5 V

* High noise immunity

* Overvoltage tolerant inputs to 5.5 V

* ±24 mA output drive (VCC = 3.0 V)

* CMOS low power dissipation

* Direct interface with TTL levels

* IOFF circuitry provides partial

74LVC1G175-nexperia.pdf