* 5 V tolerant inputs for interlacing with 5 V logic
* Wide supply voltage range from 1.2 V to 3.6 V
* CMOS low power consumption
* Direct interface with TTL levels
* Complies with JEDEC standard:
* JESD8-7A (1.65 V to 1.95 V)
* JESD8-5A (2.3 V
74LVC74A Datasheet (263.69 KB)
74LVC74A
263.69 KB
Dual d-type flip-flop.
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 11
* 22 February 2024
Product data sheet
1. General descript.
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