AM29BDS128H Datasheet | AMD

Feature - Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin - 1.8V patible I/O signals Simultaneous Read/Write operation - Data can be continuously read from one bank while executing erase/program functions in other bank - Zero latency between read and write operations - Four bank architecture: 128 Mb has 16/48/48/16 Mbit banks 64 Mb has 8/24/24/8 Mbit banks Programable Burst Interface - 2 Modes of Burst Read Operation - Linear Burst: 8, 16, and 32 words with wrap-around - Continuous Sequential Burst Sec Si TM (Secured Silicon) Sector region - Up to 128 words accessible through a mand sequence - Up to 64 factory-locked words - Up to 64 customer-lockable words Sector Architecture - Banks A and D each contain both 4 Kword sectors and 32 Kword sectors; Banks B and C contain ninety-six 32 Kword sectors - Sixteen 4 Kword boot sectors Half of the boot sectors are at the top of the address range; half are at the bottom of address range Minimum 1 million erase cycle guarantee per sector 20-year data retention at 125°C - Reliable operation for the life of the system 80-ball FBGA package...