AM29BDS643D Datasheet | AMD

feature - Provides host system with minimum possible latency by monitoring RDY s Software mand set patible with JEDEC 42.4 standards - Backwards patible with Am29F and Am29LV families s Minimum 1 million erase cycle guarantee per sector s 20-year data retention at 125°C - Reliable operation for the life of the system s Embedded Algorithms - Embedded Erase algorithm automatically preprograms and erases the entire chip or any bination of designated sectors - Embedded Program algorithm automatically writes and verifies data at specified addresses s Data# Polling and toggle bits - Provides a software method of detecting program and erase operation pletion s Erase Suspend/Resume - Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset input (RESET#) - Hardware method to reset the device for reading array data s CMOS patible inputs, CMOS patible outputs s Low VCC write inhibit s 48-Ball FBGA package This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 23709 Rev: A Amendment/+3 Issue Date: December 21, 2000 Refer to AMD’s Website (.amd.) for the latest information. P R E L I M I N A R Y GENERAL DESCRIPTION The Am29BDS643 is a 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 4,194,304 words of 16 bits each. This device uses a single VCC of 1.7 to 1.9 V to read, program, and erase...