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$0,+* PLFURQ &026 *DWH $UUD
Description ODCXXExx is a family of 1 to 24 mA, non-inverting, CMOS-level, tristate output buffer pieces with active low enables.
Logic Symbol
Truth Table
ODCXXExx EN A
PADM
EN A PADM LL L LH H HX Z
HDL Syntax Verilog .................... ODCXXExx inst_name (PADM, A, EN); VHDL...................... inst_name: ODCXXExx port map (PADM, A, EN);
Pin Loading
Pin Name
A (eq-load) EN (eq-load) PADM (pF)
ODCXXE01 5.6 4.0 4.92
ODCXXE02 7.9 5.3 4.92
ODCXXE04 7.9 5.3 4.93
Load ODCXXE08
2.3 5.5 4.93
ODCXXE12 2.3 5.5 4.93
Power Characteristics
Cell Output Drive (mA)
ODCXXE01
1
ODCXXE02
2
ODCXXE04
4
ODCXXE08
8
ODCXXE12
12
ODCXXE16
16
ODCXXE24
24
a. See page 2-15 for power equation.
ODCXXE01 Datasheet
