A63L7332 Datasheet | AMIC Technology

A63L7332 Series 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Preliminary Document Title 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Revision History Rev. No. 0.0 1.0 1.1 History Initial issue Change fast access times from 4.5/5 ns to 4.2/4.5/5.0 ns Change DC and operating characteristics ICC1 (Max.) : 300m A to 350m A ISB1 (Max.) : 25m A to 38m A Issue Date June 02, 1998 August 27, 1998 December 18, 1998 Remark Preliminary Modify 100-pin LQFP symbol y dimensions Max. in mm :0.08 → 0.1 Max. in inches : 0.003 → 0.004 December 31, 1998 PRELIMINARY (December, 1998, Version 1.2) AMIC Technology, Inc. A63L7332 Series 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output Preliminary Features n n n n n Fast access times: 4.2/4.5/5.0 ns (143/133/100 MHZ) Single +3.3V+10% or +3.3V-5% power supply Synchronous burst function Individual Byte Write control and Global Write Registered output for pipelined applications n Three separate chip enables allow wide range of options for CE control, address pipelining n Selectable BURST mode n SLEEP mode (ZZ pin) provided n Available in 100-pin LQFP package General Description The A63L7332 is a high-speed, low-power SRAM containing 4,194,304 bits of bit synchronous memory, organized as 131,072 words by 32 bits. The A63L7332 bines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output registers and a 128K X 32 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 A16), all data inputs (I/O1 - I/O32), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write ( GW ). Asynchronous inputs...