A63L93361 Datasheet | AMIC Technology

Preliminary 512K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Document Title 512K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flowthrough Data Output Revision History Rev. No. History 0.0 Initial issue Issue Date July 5, 2006 Remark Preliminary PRELIMINARY (July, 2006, Version 0.0) AMIC Technology, Corp. Preliminary 512K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Features - Fast access times: 6.5/7.5/8.0 ns(153/133/117 MHz) - Single 3.3V±5% power supply - Synchronous burst function - Individual Byte Write control and Global Write - Three separate chip enables allow wide range of options for CE control, address pipelining General Description The A63L93361 is a high-speed SRAM containing 18M bits of bit synchronous memory, organized as 512K words by 36 bits. The A63L93361 bines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 512K X 36 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 A18), all data inputs (I/O1 - I/O36), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write ( GW ). Asynchronous inputs include output enable ( OE ), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). - Selectable BURST mode - SLEEP mode (ZZ pin) provided - Available in 100-pin LQFP...