A63L73321 Datasheet | AMIC Technology

128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Preliminary Document Title 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flowthrough Data Output Revision History Rev. No. 0.0 0.1 0.2 0.3 0.4 History Initial issue Change fast access times from 8.5/9.5/10 ns to 9.5/10/12 ns Change ICC1 from 300m A to 350m A(max.) Add description for 100/91/83 MHz Add description for 2E1D at page 1 Modify waveform at page 11 Delete -9.5 & -10 part number Change -12 cycle time from 12ns to 15ns Issue Date December 14, 1998 June 9, 1999 December 19, 1999 June 20, 2000 August 29, 2001 Remark Preliminary PRELIMINARY (August, 2000, Version 0.4) AMIC Technology, Inc. 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Preliminary Features n n n n n Fast access times: 12ns at 66MHz Single +3.3V+10% or +3.3V-5% power supply Synchronous burst function Individual Byte Write control and Global Write Double-cycle enable, single-cycle deselect n Three separate chip enables allow wide range of options for CE control, address pipelining n Selectable BURST mode n SLEEP mode (ZZ pin) provided n Available in 100-pin LQFP package General Description The A63L73321 is a high-speed, low-power SRAM containing 4,194,304 bits of bit synchronous memory, organized as 131,072 words by 32 bits. The A63L73321 bines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 128K X 32 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 A16), all data inputs (I/O1 - I/O32), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write ( GW ). Asynchronous...