LP61L1008 Datasheet | AMIC Technology

Features n Single 3.3V ± 10% power supply n Access times: 12/15 ns (max.) n Current: Operating: 180m A (max.) Standby: 5m A (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL patible n Center Power/Ground Pin Configuration n mon I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2.0V (min.) n Available in 32-pin SOJ 300 mil and 32-pin s TSOP packages General Description The LP61L1008 is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL patible and allow for direct interfacing with mon system bus structures. The chip enable input is provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Product Family LP61L1008 Operating Temperature 0°C~70°C VCC Range 3.0V~3.6V Power Dissipation Speed 12/15 ns Data Retention (ICCDR, Typ.) 10µA Standby (ISB1, Typ.) 20µA Operating (ICC2, Typ.) 66m A Package Type 32L SOJ 32L s TSOP 1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 2.0V. Pin Configuration n SOJ A0 A1 A2 A3 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A0 A1 A2 A3 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 n s TSOP ~ A15 A14 A13 OE I/O8 I/O7 GND VCC I/O6 I/O5 A12 A11 A10 A9 A8 LP61L1008X ~ ~ 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 LP61L1008S (June, 2002, Version 2.0) AMIC Technology, Inc. LP61L1008 Series Block Diagram A0 VCC GND 256 X 4096 DECODER MEMORY ARRAY A14 A15 A16 I/O1 INPUT DATA CIRCUIT I/O8 COLUMN I/O CE OE...