LP61L256B
LP61L256B is 32K X 8 Bit High SPEED LOW VCC CMOS SRAM manufactured by AMIC Technology.
Features n Single +3.3 volt power supply n Access times: 12 ns (max.) n Current: Operating: 100m A (max.) Standby: 10m A (max.) n Full static operation, no clock or refreshing required n n n n All inputs and outputs directly TTL patible mon I/O using three-state output Data retention voltage: 2V (min.) Available in 28-pin SOJ and TSOP packages
General Description
The LP61L256B is a high-speed, low-power 262,144-bit static random access memory organized as 32,768 words by 8 bits that operates on a single 3.3V power supply. Input and three-state outputs are TTL patible and allow for direct interfacing with mon system bus structures. Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2V.
Pin Configurations n SOJ n TSOP
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE A13 A8 14 1
LP61L256BV
A9 A11 OE A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 15
Pin No. Pin Name Pin No. Pin Name
1 OE 15 A2
2 A11 16 A1
3 A9 17 A0
4 A8 18 I/O 1
5 A13 19 I/O 2
6 WE 20
7 VCC 21
8 A14 22 I/O 4
9 A12 23 I/O 5
10 A7 24 I/O 6
11 A6 25 I/O 7
12 A5 26 I/O 8
13 A4 27 CE
14 A3 28 A10
I/O 3 GND
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP61L256B Series
Block Diagram
A0 A5 A7 A9 A12 ROW DECODER 256 X 1024 MEMORY ARRAY VCC GND
I/O1 COLUMN I/O INPUT DATA CIRCUIT COLUMN DECODER I/O8
A1
A4 A8 A13 A14
CE OE WE CONTROL CIRCUIT
Pin Descriptions -SOJ
Pin No. 1
- 10, 21, 23
- 26...
