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LP61L256C - 32K X 8 BIT HIGH SPEED CMOS SRAM

General Description

The LP61L256C is a high-speed, low-power 262,144-bit static random access memory organized as 32,768 words by 8 bits and operates on a single 3.3V power supply.

It is built using high performance CMOS process.

Key Features

  • n Single +3.3V power supply n Access times: 12/15 ns (max. ) n Current: Operating: 120mA (max. ) Standby: 5mA (max. ) n Full static operation, no clock or refreshing required n n n n All inputs and outputs are directly TTL compatible Common I/O using three-state output Data retention voltage: 2V (min. ) Available in 28-pin SOJ package 32K X 8 BIT HIGH SPEED CMOS SRAM General.

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Datasheet Details

Part number LP61L256C
Manufacturer AMIC Technology
File Size 110.08 KB
Description 32K X 8 BIT HIGH SPEED CMOS SRAM
Datasheet download datasheet LP61L256C Datasheet

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Other Datasheets by AMIC Technology

Part Number Description
LP61L256B 32K X 8 Bit High SPEED LOW VCC CMOS SRAM
LP61L1008 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
LP61L1008A 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
LP61L1024 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
LP621024D 128K X 8 BIT CMOS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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LP61L256C Preliminary Document Title 32K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. 0.0 32K X 8 BIT HIGH SPEED CMOS SRAM History Initial issue Issue Date November 9, 2001 Remark Preliminary PRELIMINARY (November, 2001, Version 0.0) AMIC Technology, Inc. LP61L256C Preliminary Features n Single +3.3V power supply n Access times: 12/15 ns (max.) n Current: Operating: 120mA (max.) Standby: 5mA (max.) n Full static operation, no clock or refreshing required n n n n All inputs and outputs are directly TTL compatible Common I/O using three-state output Data retention voltage: 2V (min.