LP61L256C Datasheet | AMIC Technology

Features n Single +3.3V power supply n Access times: 12/15 ns (max.) n Current: Operating: 120m A (max.) Standby: 5m A (max.) n Full static operation, no clock or refreshing required n n n n All inputs and outputs are directly TTL patible mon I/O using three-state output Data retention voltage: 2V (min.) Available in 28-pin SOJ package 32K X 8 BIT HIGH SPEED CMOS SRAM General Description The LP61L256C is a high-speed, low-power 262,144-bit static random access memory organized as 32,768 words by 8 bits and operates on a single 3.3V power supply. It is built using high performance CMOS process. Inputs and three-state outputs are TTL patible and allow for direct interfacing with mon system bus structures. Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations n SOJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PRELIMINARY (November, 2001, Version 0.0) AMIC Technology, Inc. LP61L256C Series Block Diagram A0 A5 A6 A7 A9 A10 A11 A12 ROW DECODER 256 X 1024 MEMORY ARRAY VCC GND I/O0 COLUMN I/O INPUT DATA CIRCUIT COLUMN DECODER I/O7 A1 A2 A3 A4 A8 A13 A14 CE OE WE CONTROL CIRCUIT Pin Descriptions - SOJ Pin No. 1 - 10, 21, 23 - 26 11 - 13, 15 - 19 14 28 20 22 27 Symbol A0 - A14 I/O0 - I/O7 GND VCC CE OE WE Description Address Inputs Data Inputs/Outputs Ground Power Supply Chip Enable Output Enable Write Enable PRELIMINARY (November, 2001, Version 0.0) AMIC Technology, Inc. LP61L256C Series Remended DC Operating Conditions (TA = 0°C to + 70°C) Symbol VCC GND VIH VIL CL Parameter Supply Voltage Ground Input High Voltage Input Low (1) Voltage Output Load Min. 3.0 0 2.2 -0.5 Typ. 3.3 0 0 Max. 3.6 0 VCC + 0.3 +0.8 30 Unit V V V V p F Absolute Maximum Ratings- VCC to GND...