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LP62S16512A - 8M BIT (512K x 16 / 1M x 8) LOW VOLTAGE CMOS SRAM

Datasheet Summary

Description

The LP62S16512A is a low operating current 8,388,608-bit static random access memory organized as 524,288 words by 16 bits and operates on low power voltage from 2.7V to 3.6V.

It is built using AMIC's high performance CMOS process.

Features

  • Operating voltage: 2.7V to 3.6V.
  • Access times: 55/70 ns (max. ).
  • Current: Very low power version: Operating: 50mA (max. ) Standby: 20μA (max. ).
  • Full static operation, no clock or refreshing required.
  • All inputs and outputs are directly TTL-compatible.
  • Common I/O using three-state output.
  • Data retention voltage: 2.0V (min. ).
  • Available in 48-pin TSOP (I) and 48-ball CSP (6 x 8 mm) packages.
  • All Pb-free (Lead-free) prod.

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Datasheet Details

Part number LP62S16512A
Manufacturer AMIC Technology
File Size 169.43 KB
Description 8M BIT (512K x 16 / 1M x 8) LOW VOLTAGE CMOS SRAM
Datasheet download datasheet LP62S16512A Datasheet
Additional preview pages of the LP62S16512A datasheet.

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Full PDF Text Transcription

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LP62S16512A Series Preliminary 8M BIT (512K x 16 / 1M x 8) LOW VOLTAGE CMOS SRAM Document Title 8M BIT (512K x 16 / 1M x 8) LOW VOLTAGE CMOS SRAM Revision History Rev. No. History 0.0 Initial issue Issue Date Remark November 13, 2014 Preliminary PRELIMINARY (November, 2014, Version 0.0) AMIC Technology, Corp. LP62S16512A Series Preliminary 8M BIT (512K x 16 / 1M x 8) LOW VOLTAGE CMOS SRAM Features „ Operating voltage: 2.7V to 3.6V „ Access times: 55/70 ns (max.) „ Current: Very low power version: Operating: 50mA (max.) Standby: 20μA (max.) „ Full static operation, no clock or refreshing required „ All inputs and outputs are directly TTL-compatible „ Common I/O using three-state output „ Data retention voltage: 2.0V (min.
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