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AT32M416 - 32-bit MCU

Download the AT32M416 datasheet PDF. This datasheet also covers the AT32M412 variant, as both devices belong to the same 32-bit mcu family and are provided as variant models within a single manufacturer datasheet.

Description

9 2 Functionality overview 12 2.1 ARM®Cortex®-M4 with FPU 12 2.2 Memory 12 2.2.1 Flash12 2.2.2 Memory protection unit (MPU) 12 2.2.3 SRAM 12 2.3 Interrupts 13 2.3.1 Nested vectored interrupt controller (NVIC)13 2.3.2 External interrupts (EXINT) 13 2.4 Power control (PWC) 13 2.4.1 Power supp

Features

  • Core: ARM® 32-bit Cortex®-M4 CPU with FPU.
  • 180 MHz maximum frequency, with a memory protection unit (MPU), single-cycle multiplication and hardware division.
  • Floating point unit (FPU).
  • DSP instructions.
  • Memories.
  • 64 to 128 Kbytes of Flash memory.
  • 28 Kbytes of boot memory used as a Bootloader or as a general instruction/data memory (one-time configurable).
  • 1 Kbyte of OTP memory.
  • sLib: configurable part of main Flash as a l.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AT32M412-ARTERY.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AT32M416
Manufacturer ARTERY
File Size 2.61 MB
Description 32-bit MCU
Datasheet download datasheet AT32M416 Datasheet

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Other Datasheets by ARTERY

Part Number Description
AT32M412 32-bit MCU
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AT32A423 32-bit MCU+FPU
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AT32F403 32-bit MCU+FPU

Full PDF Text Transcription

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AT32M412/416 Series Datasheet ARM®-based 32-bit Cortex®-M4 MCU with FPU, 64 to 128 KB Flash, sLib, 11 timers, 8 communication interfaces (1 CAN or CANFD), 2 ADCs, 2 DACs, 2 CMPs, 4 OPs Features  Core: ARM® 32-bit Cortex®-M4 CPU with FPU − 180 MHz maximum frequency, with a memory protection unit (MPU), single-cycle multiplication and hardware division − Floating point unit (FPU) − DSP instructions  Memories − 64 to 128 Kbytes of Flash memory − 28 Kbytes of boot memory used as a Bootloader or as a general instruction/data memory (one-time configurable) − 1 Kbyte of OTP memory − sLib: configurable part of main Flash as a library area with code executable but secured, non-readable − 16 Kbytes of SRAM  Power control (PWC) − 2.4 to 3.
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