MT5C2564 Datasheet | ASI

SRAM Austin Semiconductor, Inc. 64K x 4 SRAM SRAM MEMORY ARRAY AVAILABLE AS MILITARY SPECIFICATIONS - SMD 5962-88681 - MIL-STD-883 PIN ASSIGNMENT (Top View) Features - - - - High Speed: 15, 20, 25, 35, 45, 55, and 70 Battery Backup: 2V data retention Low power standby High-performance, low-power, CMOS double-metal process - Single +5V (+10%) Power Supply - Easy memory expansion with CE - All inputs and outputs are TTL patible A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CE Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Vcc A15 A14 A13 A12 A11 A10 DQ4 DQ3 DQ2 DQ1 WE A1 A0 NC Vcc NC 3 2 1 28 27 A2 A3 A4 A5 A6 A7 A8 A9 CE 4 5 6 7 8 9 10 11 12 26 25 24 23 22 21 20 19 18 A15 A14 A13 A12 A11 A10 DQ4 DQ3 DQ2 24-Pin DIP (C) (300 MIL) 28-Pin LCC (EC) 13 14 15 16 17 DQ1 WE NC Vss NC OPTIONS - Timing 15ns access 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access - Package(s) Ceramic DIP (300 mil) Ceramic LCC MARKING -15 -20 -25 -35 -45 -55- -70- GENERAL DESCRIPTION The Austin Semiconductor SRAM family employs high-speed, low-power CMOS and are fabricated using doublelayer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE) on all organizations. This enhancement can place the outputs in High-Z for additional flexibility in system design. The x4 configuration Features mon data input and output. Writing to these devices is acplished when write enable (WE) and CE inputs are both LOW. Reading is acplished when WE remains HIGH and CE goes LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. These devices operate from a single +5V power supply and all inputs and outputs are fully TTL patible. C...