MT5C2564 Overview
The MT5C2564 is organized as a 65,536 x 4 SRAM using a four-transistor memory cell with a high-speed, low-power CMOS proc.
MT5C2564 Key Features
- High speed: 10, 12, 15,20,25 and 35ns
- High-performance, low-power, CMOS double-metal
- Single +5V ±10% power supply
- Easy memory expansion with CE option
- All inputs and outputs are TTL-patible
- Timing IOns access 12ns access 15ns access 20ns access 25ns access 35ns access
- Packages Plastic DIP (300 mil) Plastic SOJ (300 mil)
- 10 -12 -15 -20 -25 -35
- 2V data retention
- Lowpower
