ASI MT5C6405
The Austin Semiconductor SRAM family employs high-speed, low-power CMOS designs using a four-transistor memory cell. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) and output enable (OE\) capability.| Part No. | MT5C6405 |
|---|---|
| Datasheet | MT5C6405 Download |
| Manufacturer |  ASI |
| Description | 16K x 4 SRAM SRAM MEMORY ARRAY |
| Buy | Stock & Price |
FEATURES
● High Speed: 12, 15, 20, 25, 35, 45, 55, and 70ns● Battery Backup: 2V data retention
● High-performance, low-power CMOS double-metal process
● Single +5V (+10%) Power Supply
● Easy memory expansion with CE\
● All inputs and outputs are TTL compatible 28-Pin LCC (EC) A5 NC NC Vcc NC 3 2 1 28 27 OPTIONS
● Timing 12ns access 15ns access 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access
● Package(s) Ceramic DIP (300 mil) Ceramic LCC MARKING -12 -15 -20 -25 -35 -45* -55* -70* A6 4 A7 5 A8 6 A9 7 A10 8 A11 9 A12 10 A13 11 CE\ 12 26 25 24 23 22 21 20 19 18 NC A4 A3 A2 A1 A0 DQ4 DQ3 DQ2 13 14 15 16 17 DQ1 WE\ NC Vss OE\ C EC No. 106 No. 204
GENERAL DESCRIPTION
Austin Semiconductor SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW.
