MT5C6404 Datasheet | ASI

FEATURES - Speeds: 12, 15, 20, 25, 35, 45, 55, and 70ns - Battery Backup: 2V data retention - High-performance, low-power CMOS double-metal process - Single +5V (+10%) Power Supply - Easy memory expansion with CE - All inputs and outputs are TTL patible GENERAL DESCRIPTION The Austin Semiconductor SRAM family employs high-speed, low-power CMOS designs using a four-transistor memory cell. Austin Semiconductor SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE) on all organizations. This enhancement can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is acplished when write enable (WE) and CE inputs are both LOW. Reading is acplished when WE remains HIGH and CE goes LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL patible. OPTIONS - Timing 12ns access 15ns access 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access - Package(s) Ceramic DIP (300 mil) MARKING -12 -15 -20 -25 -35 -45- -55- -70- No. 105 - Operating Temperature Ranges Industrial (-40o C to +85o C) IT Military (-55o C to +125o C) XT - 2V data retention/low power L - Electrical characteristics identical to those provided for the 35ns access devices. For more products and information please visit our web site at .austinsemiconductor. MT5C6404 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SRAM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM VCC GND ROW DECODER A A A A A A DQ4 I/O CONTROL 65,536-BIT MEMORY ARRAY CE (LSB) COLUMN DECODER (LSB) POWER...