Datasheet Summary
Features
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.. 80C51 Core Architecture 256 Bytes of On-chip RAM 1K Bytes of On-chip ERAM 32K Bytes of On-chip Flash Memory
- Data Retention: 10 Years at 85°C Read/Write Cycle: 10K 2K Bytes of On-chip Flash for Bootloader 2K Bytes of On-chip EEPROM Read/Write Cycle: 100K 14-sources 4-level Interrupts Three 16-bit Timers/Counters Full Duplex UART patible 80C51 Maximum Crystal Frequency 40 MHz
- In X2 Mode, 20 MHz (CPU Core, 40 MHz) Five Ports: 32 + 2 Digital I/O Lines Five-channel 16-bit PCA with:
- PWM (8-bit)
- High-speed Output
- Timer and Edge Capture Double Data Pointer 21-bit WatchDog Timer (7 Programmable Bits) A 10-bit Resolution Analog to...