AT60142ET Datasheet | Atmel

Features - Operating Voltage: 3.3V - Access Time: - - - - - - - - - - - 15 ns (Preview) for 3.3V biased only (AT60142E) - 17 ns and 20 ns for 5V Tolerant (AT60142ET) Very Low Power Consumption - Active: 810 m W (Max) @ 15 ns - Standby: 215 µW (Typ) Wide Temperature Range: -55 to +125°C 500 Mils Width Package TTL-patible Inputs and Outputs Asynchronous Designed on 0.25 Micron Process No Single Event Latch Up below LET Threshold of 80 Me V/mg/cm 2 Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019 500 Mils Wide FP36 Package ESD Better than 4000V Rad Hard 512K x 8 Very Low Power CMOS SRAM AT60142E AT60142ET Description The AT60142E/ET are very low power CMOS static RAM organized as 524 288 x 8 bits. Atmel brings the solution to applications where fast puting is as mandatory as low consumption, such as aerospace electronics, portable instruments, or embarked systems. Utilizing an array of six transistors (6T) memory cells, the AT60142E/ET bine an extremely low standby supply current (Typical value = 65 µ A) with a fast access time at 15 ns over the full military temperature range. The high stability of the 6T cell provides excellent protection against soft errors due to noise. The E version is biased at 3.3 V and is not 5V tolerant: it is available to 15(1) and 20 ns specification. The ET(1) version is a variant allowing for 5V tolerance: it is available in 17 ns and 20 ns specification. The AT60142E/ET are processed according to the methods of the latest revision of the MIL PRF 38535 or ESA SCC 9000. It is produced on a radiation hardened 0.25 µm CMOS process. Note: 1. Preliminary: contact factory for availability. Rev. 4156F- AERO- 06/04 AT60142E/ET Block Diagram Pin Configuration A0 A1 A2 A3 A4 CS I/O1 I/O2 Vcc GND I/O3 I/O4 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 3 6 p i n F l a t p a c k 5 0 0 M i l s 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O8 I/O7 GND Vcc I/O6 I/O5...