Datasheet4U Logo Datasheet4U.com

AT91SC25672RC - 32-bit Secure Microcontroller

Datasheet Summary

Description

The AT91SC25672RC is a low-power, high-performance, 32-bit RISC microcontroller with ROM program memory, EEPROM data memory, and cryptographic accelerator, based on the new ARM SC100 advanced secure processor.

The SC100 embedded core is the first member of the ARM SecurCore family.

Features

  • General.
  • Based on the ARM® SC100™ SecurCore™ 32-bit RISC Processor.
  • Two Instruction Sets.
  • ARM High-performance 32-bit Instruction Set.
  • Thumb® High-code-density 16-bit Instruction Set 4-Gbyte Linear Address Space Von Neumann Load/Store Architecture.
  • Single 32-bit Data Bus for Instructions and Data 3-stage Pipeline Architecture.
  • Fetch, Decode and Execute S.

📥 Download Datasheet

Datasheet preview – AT91SC25672RC

Datasheet Details

Part number AT91SC25672RC
Manufacturer ATMEL Corporation
File Size 58.30 KB
Description 32-bit Secure Microcontroller
Datasheet download datasheet AT91SC25672RC Datasheet
Additional preview pages of the AT91SC25672RC datasheet.

📁 Similar Datasheet

  • AT91SAM9261 - Microcontrollers (Atmel)
  • AT91SAM9M10 - AT91 ARM Thumb-based Microcontrollers (ATMEL)
  • AT912AXS - High Speed 12-Bit A/D Converter (Anloy Technologies)
  • AT9173 - Bus Termination Regulator (Attansic)
  • AT9173 - Bus Termination Regulator (AME)
  • AT91C140 - Microcontrollers (ATMEL)
  • AT91FR40162SB - AT91 ARM Thumb-based Microcontrollers (ATMEL)
  • AT91M40807 - AT91 ARM Thumb Microcontroller (ATMEL)
  • AT91RM9200 - MPU (ATMEL)
  • AT90-0001 - Digital Attenuator/ 31.0 dB/ 5-Bit/ TTL Driver/ DC-6.0 GHz (Tyco Electronics)
Other Datasheets by ATMEL Corporation

Full PDF Text Transcription

Click to expand full text
Features General • Based on the ARM® SC100™ SecurCore™ 32-bit RISC Processor • Two Instruction Sets • • • • • • • • • – ARM High-performance 32-bit Instruction Set – Thumb® High-code-density 16-bit Instruction Set 4-Gbyte Linear Address Space Von Neumann Load/Store Architecture – Single 32-bit Data Bus for Instructions and Data 3-stage Pipeline Architecture – Fetch, Decode and Execute Stages 8-bit, 16-bit, and 32-bit Data Types On-chip Programmable System Clock up to 50 MHz Very Low Power Consumption: – Industry Leader in MIPS/Watt – Low-power Idle and Power-down Modes Bond Pad Locations Conforming to ISO 7816-2 ESD Protection to ± 6000V Operating Ranges: 2.7V to 5.
Published: |