AT91SC512384RCT Datasheet | Atmel

Features General - Based on the ARM® SC100 Secure Core 32-bit RISC Processor - Two Instruction Sets - - - - - - - - - ARM High-performance 32-bit Instruction Set - Thumb® High-code-density 16-bit Instruction Set Von Neumann Load/Store Architecture - Single 32-bit Data Bus for Instructions and Data 3-stage Pipeline Architecture - Fetch, Decode, and Execute Stages 8-bit, 16-bit, and 32-bit Data Types On-chip Programmable System Clock up to 50MHz Very Low Power Consumption - Industry Leader in MIPS/Watt - Low power Idle and Power down Modes Bond Pad Locations Confirming to ISO7816-2 ESD Protection to ±6000V Operating ranges: 1.62V to 5.5V, GSM/3G pliant, PC Industry patible, EMV 32-bit Secure Microcontrollers Memory - 512K Bytes of ROM Program Memory - 384K Bytes of EEPROM, Including 256 OTP Bytes - - - - - Typically More than 500,000 Write/Erase Cycles at a Temperature of 25o C - 10 Years Data Retention EEPROM Erase Only Mode Write EEPROM With or Without Autoerase 24K Bytes of RAM (2K Bytes shared with Adv X  crypto processor) 32K Bytes of ROM dedicated to Atmel’s crypto Library AT91SC 512384RCT Summary Peripherals - One ISO 7816 Controller - Up to 625kbps at 5 MHz - Serial Peripheral Interface (SPI) Controller (up to 20MHz) - USB Interface (5 Endpoints) - USB V2.0 Full-speed (12Mbps), Suspend/Resume Modes Supported - 4 Configurable Endpoints in Addition to Endpoint EP0 - Dynamic Pull-up Attachment USB_IC (Inter Chip) 0.8e Interface Interface for External NAND Flash Memory Single Wire Interface (Digital Interface to RF front end chip) Two 16-bit Timers Random Number Generator (RNG) 2-level, 15-vector Interrupt Controller Hardware DES and Triple DES (DPA Resistant) Checksum Accelerator CRC 16/32 Engine 32-bit Cryptographic Accelerator for Public Key Operations - RSA, DSA, ECC, Diffie-Hellman High performance Hardware Java Card Accelerator - - - - - - - - - - - Security - -...