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Features
General
• Based on the ARM® SC100 SecureCore 32-bit RISC Processor • Two Instruction Sets • • • • • • • •
– ARM High-performance 32-bit Instruction Set – Thumb® High-code-density 16-bit Instruction Set Von Neumann Load/Store Architecture – Single 32-bit Data Bus for Instructions and Data 3-stage Pipeline Architecture – Fetch, Decode, and Execute Stages 8-bit, 16-bit, and 32-bit Data Types On-chip Programmable System Clock up to 50MHz Very Low Power Consumption – Industry Leader in MIPS/Watt – Low power Idle and Power down Modes Bond Pad Locations Confirming to ISO7816-2 ESD Protection to ±6000V Operating ranges: 1.62V to 5.
AT91SC512384RCT Datasheet
