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AS7C251MNTD18A - 2.5V 1M x 18 Pipelined SRAM

General Description

The AS7C251MNTD18A family is a high performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words × 18 bits and incorporates a LATE LATE Write.

Key Features

  • Organization: 1,048,576 words × 18 bits.
  • NTD™architecture for efficient bus operation.
  • Fast clock speeds to 166 MHz.
  • Fast clock to data access: 3.5/3.8 ns.
  • Fast OE access time: 3.5/3.8 ns.
  • Fully synchronous operation.
  • Asynchronous output enable control.
  • Available in 100-pin TQFP package www. DataSheet4U. com.
  • Individual byte write and global write.
  • Clock enab.

📥 Download Datasheet

Datasheet Details

Part number AS7C251MNTD18A
Manufacturer Alliance Semiconductor Corporation
File Size 480.76 KB
Description 2.5V 1M x 18 Pipelined SRAM
Datasheet download datasheet AS7C251MNTD18A Datasheet

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Other Datasheets by Alliance Semiconductor Corporation

Part Number Description
AS7C251MNTD32A (AS7C251MNTD32A / AS7C251MNTD36A) 2.5V 1M x 32/36 Pipelined SRAM
AS7C251MNTD36A (AS7C251MNTD32A / AS7C251MNTD36A) 2.5V 1M x 32/36 Pipelined SRAM
AS7C251MNTF18A 2.5V 1M x 18 Flowthrough Synchronous SRAM
AS7C251MNTF32A (AS7C251MNTF32A / AS7C251MNTF36A) 2.5V 1M x 32/36 Flowthrough SRAM
AS7C251MNTF36A (AS7C251MNTF32A / AS7C251MNTF36A) 2.5V 1M x 32/36 Flowthrough SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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December 2004 ® AS7C251MNTD18A 2.5V 1M x 18 Pipelined SRAM with NTDTM Features • Organization: 1,048,576 words × 18 bits • NTD™architecture for efficient bus operation • Fast clock speeds to 166 MHz • Fast clock to data access: 3.5/3.8 ns • Fast OE access time: 3.5/3.8 ns • Fully synchronous operation • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • Individual byte write and global write • • • • • • Clock enable for operation hold Multiple chip enables for easy expansion 2.5V core power supply Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation Logic block diagram A[19:0] 20 D Address register burst logic Q 20 CLK CE0 CE1 CE2 R/W BWa BWb ADV / LD LBO ZZ D Q 20 Write delay addr.