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AS7C251MNTD36A - (AS7C251MNTD32A / AS7C251MNTD36A) 2.5V 1M x 32/36 Pipelined SRAM

Download the AS7C251MNTD36A datasheet PDF. This datasheet also covers the AS7C251MNTD32A variant, as both devices belong to the same (as7c251mntd32a / as7c251mntd36a) 2.5v 1m x 32/36 pipelined sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The AS7C251MNTD32A/36A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words × 32 or 36 bits and incorporates a LATE LATE Write.

Key Features

  • Organization: 1,048,576 words × 32 or 36 bits.
  • NTD™architecture for efficient bus operation.
  • Fast clock speeds to 200 MHz.
  • Fast clock to data access: 3.2/3.5/3.8 ns.
  • Fast OE access time: 3.2/3.5/3.8 ns.
  • Fully synchronous operation.
  • pipelined mode www. DataSheet4U. com.
  • Common data inputs and data outputs.
  • Asynchronous output enable control Logic block diagram A[19:0] 20 D.
  • Available in 100-pin TQFP packages.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AS7C251MNTD32A_AllianceSemiconductorCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AS7C251MNTD36A
Manufacturer Alliance Semiconductor Corporation
File Size 481.09 KB
Description (AS7C251MNTD32A / AS7C251MNTD36A) 2.5V 1M x 32/36 Pipelined SRAM
Datasheet download datasheet AS7C251MNTD36A Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
January 2005 ® AS7C251MNTD32A AS7C251MNTD36A 2.5V 1M × 32/36 Pipelined SRAM with NTDTM Features • Organization: 1,048,576 words × 32 or 36 bits • NTD™architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns • Fast OE access time: 3.2/3.5/3.8 ns • Fully synchronous operation • pipelined mode www.DataSheet4U.com • Common data inputs and data outputs • Asynchronous output enable control Logic block diagram A[19:0] 20 D • Available in 100-pin TQFP packages • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 2.