AS7C331FT18A Datasheet | Alliance Semiconductor Corporation

Features - - - - - - - Organization: 1,048,576 words x18 bits Fast clock to data access: 6.8/7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available 100-pin TQFP packages Individual byte write and global write - - - - - - Multiple chip enables for easy expansion 3.3 V core power supply 2.5 V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control mon data inputs and data outputs Snooze mode for reduced power-standby .. Logic block diagram CLK ADV ADSC ADSP A[19:0] CLK CS CLR Burst logic 20 18 20 Q D CS Address register CLK 1M x 18 Memory array 18 18 GWE BWb BWE BWa CE0 CE1 CE2 D DQb CLK D DQa Q Byte Write registers Byte Write registers CLK D CE CLK ZZ Enable register Output buffers Input registers Power down D Enable Q delay register CLK OE DQ[a,b] Selection guide Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) -68 7.5 6.8 285 90 60 -75 8.5 7.5 275 90 60 -85 10 8.5 250 80...