AS7C332MFT18A Datasheet | Alliance Semiconductor Corporation

December 2004 ® 3.3V 2M × 18 Flow-through synchronous SRAM Features - - - - - - - Organization: 2,097152 words × 18 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write - - - - - - Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby mon data inputs and data outputs .. Logic block diagram CLK ADV ADSC ADSP A[20:0] CLK CS CLR Burst logic CS Address register CLK 19 21 2M x 18 Memory array 18 18 GWE BWb BWE BWa CE0 CE1 CE2 D DQb CLK D DQa Q Byte Write registers Byte Write CLK D registers Enable register CE CLK ZZ Output registers Input registers Power down D Enable Q delay...